The present invention relates to integrated circuit device manufacture, and more particularly, but not exclusively, relates to techniques to provide electrical isolation structures for an integrated circuit.
Shallow Trench Isolation (STI) is becoming a favored technology to electrically isolate regions of an integrated circuit having components with submicron critical dimensions. Generally, STI involves forming trenches in an integrated circuit substrate, then filling these trenches with a dielectric material. One approach has been to fill the trenches with Tetraethylorthosilicate (TEOS) using a Low Pressure Chemical Vapor Deposition (LPCVD) procedure as described, for example, in U.S. Pat. No. 5,691,215 to Dai et al. However, this approach tends to leave too many voids and other discontinuities as integrated circuits are scaled down to include components having a critical dimension equal to or less than 0.25 microns.
Consequently, other approaches have been investigated. For example, U.S. Pat. No. 5,728,621 to Zheng et al. describes a High Density Plasma (HDP) deposition of a dielectric material to fill isolation trenches. Still, one drawback of this approach is poor local planarity over topography of various sizes and pattern densities. Generally, HDP deposition results in a thicker material over large, expansive features between the trenches, and a thinner material over narrow trenches that may be narrowly spaced from one another. Due to this nonuniformity, subsequent planarization procedures, such as Chemical-Mechanical Polishing (CMP), frequently result in the advertent reduction in the thickness of a layer or film beneath the HDP material in regions where it is thin, or the failure to remove some of the HDP material in regions where it is thick.
One attempt to solve this problem has been a "reverse mask" scheme. This scheme includes placement of a mask over areas where the HDP material is thinner to selectively etch away the thicker regions until a generally uniform HDP material thickness results. The reverse mask is then removed and the device planarized to desired specifications. Unfortunately, the reverse mask process significantly complicates manufacturing, adding several device processing phases. Concomitantly, manufacturing costs generally increase. Thus, there is a demand for better techniques to provide isolation structures.